Index of /pub/educational/Coursera - VLSI CAD - Logic to Layout by Rob A. Rutenbar - University of Illinois at Urbana-Champaign/Lectures/10_Timing_Analysis_Week_8/
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01_12.1_Basics_7-13.mp4 23-Jul-2026 14:08 15699134
01_12.1_Basics_7-13.srt 23-Jul-2026 14:07 11490
01_12.1_Basics_7-13.txt 23-Jul-2026 14:07 7679
02_12.2_Logic-Level_Timing-_Basic_Assumptions__..> 23-Jul-2026 14:08 37516390
02_12.2_Logic-Level_Timing-_Basic_Assumptions__..> 23-Jul-2026 14:07 51231
02_12.2_Logic-Level_Timing-_Basic_Assumptions__..> 23-Jul-2026 14:07 33700
03_12.3_Logic-Level_Timing-_STA_Delay_Graph_ATs..> 23-Jul-2026 14:08 31914543
03_12.3_Logic-Level_Timing-_STA_Delay_Graph_ATs..> 23-Jul-2026 14:07 43392
03_12.3_Logic-Level_Timing-_STA_Delay_Graph_ATs..> 23-Jul-2026 14:07 28486
04_12.4_Logic-Level_Timing-_A_Detailed_Example_..> 23-Jul-2026 14:07 16558914
04_12.4_Logic-Level_Timing-_A_Detailed_Example_..> 23-Jul-2026 14:07 14823
04_12.4_Logic-Level_Timing-_A_Detailed_Example_..> 23-Jul-2026 14:07 9577
05_12.5_Logic-Level_Timing-_Computing_ATs_RATs_..> 23-Jul-2026 14:08 34650442
05_12.5_Logic-Level_Timing-_Computing_ATs_RATs_..> 23-Jul-2026 14:07 43280
05_12.5_Logic-Level_Timing-_Computing_ATs_RATs_..> 23-Jul-2026 14:07 28444
06_12.6_Interconnect_Timing-_Electrical_Models_..> 23-Jul-2026 14:08 24624914
06_12.6_Interconnect_Timing-_Electrical_Models_..> 23-Jul-2026 14:07 27280
06_12.6_Interconnect_Timing-_Electrical_Models_..> 23-Jul-2026 14:07 18044
07_12.7_Interconnect_Timing-_The_Elmore_Delay_M..> 23-Jul-2026 14:08 18788425
07_12.7_Interconnect_Timing-_The_Elmore_Delay_M..> 23-Jul-2026 14:08 21612
07_12.7_Interconnect_Timing-_The_Elmore_Delay_M..> 23-Jul-2026 14:08 14301
08_12.8_Interconnect_Timing-_Elmore_Delay_Examp..> 23-Jul-2026 14:08 26282338
08_12.8_Interconnect_Timing-_Elmore_Delay_Examp..> 23-Jul-2026 14:07 23385
08_12.8_Interconnect_Timing-_Elmore_Delay_Examp..> 23-Jul-2026 14:07 15479