1 00:00:00,5 --> 00:00:08,436 [SOUND]. 2 00:00:08,436 --> 00:00:11,816 So here in lecture 9.8, we're going to continue our exploration of Analytical 3 00:00:11,816 --> 00:00:14,934 Placement. The really amazing thing about the 4 00:00:14,934 --> 00:00:19,94 quadratic wire length model is that I can write a giant equation for where the 5 00:00:19,94 --> 00:00:23,654 logic gates go. And I can solve it using some calculus 6 00:00:23,654 --> 00:00:28,210 and some linear algebra, and actually get as the solution to this equation, done 7 00:00:28,210 --> 00:00:32,782 numerically, a placement. That's pretty amazing. 8 00:00:32,782 --> 00:00:36,750 The problem is that because we made some key assumptions, and one of those 9 00:00:36,750 --> 00:00:40,656 assumptions is that the gates are dimensionless points, we don't actually 10 00:00:40,656 --> 00:00:45,900 get a legal placement. So, unlike the intricate methods where we 11 00:00:45,900 --> 00:00:49,680 had a grid and every gate was located in one and only one cell on the grid, when 12 00:00:49,680 --> 00:00:53,460 we're done with a quadratic style analytical placement, the gates can be in 13 00:00:53,460 --> 00:00:58,578 one big blob in on little corner of the chip. 14 00:00:58,578 --> 00:01:02,10 We're going to have to do something, a different kind of an optimization step to 15 00:01:02,10 --> 00:01:05,757 kind of spread them out. And interestingly enough, we're going to 16 00:01:05,757 --> 00:01:09,126 do something that's kind of recursive. We're going to chop the chip up into 17 00:01:09,126 --> 00:01:11,976 pieces. We're going to figure out which piece the 18 00:01:11,976 --> 00:01:15,230 gates need to go in. And we're going to formulate an 19 00:01:15,230 --> 00:01:18,805 increasing series of smaller quadratic placement problems, each of which is 20 00:01:18,805 --> 00:01:22,923 going to, sort of in a finer, and finer, and finer way. 21 00:01:22,923 --> 00:01:27,220 Put the gates in the right place. So, this is recursive partitioning using 22 00:01:27,220 --> 00:01:30,610 a quadratic style analytical placer model. 23 00:01:30,610 --> 00:01:35,108 Let's go see how that works. We just introduced the full, sort of 24 00:01:35,108 --> 00:01:40,276 mathematical model and solution technique for representing wire length as quadratic 25 00:01:40,276 --> 00:01:45,205 clique wire-length model. pretending all the gates are 26 00:01:45,205 --> 00:01:49,897 dimensionless points, optimizing the quadratic wire-length, which turns into a 27 00:01:49,897 --> 00:01:54,816 set of matrix solutions. An a matrix and a bx vector, an a matrix 28 00:01:54,816 --> 00:02:00,880 and a by vector, and we solve that and we get x-coordinates and y-coordinates. 29 00:02:00,880 --> 00:02:03,400 What does it look like? It looks like this. 30 00:02:03,400 --> 00:02:07,430 This is a small IBM ASIC a reasonably famous public benchmark with a few 31 00:02:07,430 --> 00:02:11,49 thousand gates. And you immediately see the problem. 32 00:02:11,49 --> 00:02:13,862 This doesn't look like a placement at all. 33 00:02:13,862 --> 00:02:18,284 this is this big smear of gates right in the middle of the chip, and this little 34 00:02:18,284 --> 00:02:24,127 sprinkling of gates in other places. this is a big problem, a new problem an 35 00:02:24,127 --> 00:02:27,732 interesting problem, maybe an unexpected problem. 36 00:02:27,732 --> 00:02:31,242 The quadratic wire-length model minimizes the wire-length for netlists in a 37 00:02:31,242 --> 00:02:34,914 numerical way, but it totally ignores the fact that the gates have a physical size 38 00:02:34,914 --> 00:02:40,854 and they can't be on top of each other. There is, and this is the beautiful thing 39 00:02:40,854 --> 00:02:46,514 about the quadratic wire-length model. There is one solution that minimizes the 40 00:02:46,514 --> 00:02:51,404 sum of the quadratic wire-lengths. And when you solve it, you get what you 41 00:02:51,404 --> 00:02:54,801 get. And you don't necessarily get the gates 42 00:02:54,801 --> 00:02:58,670 lining up in rows not on top of each other. 43 00:02:58,670 --> 00:03:01,602 I've got to fix this. And it turns out there's a lovely 44 00:03:01,602 --> 00:03:06,10 strategy for doing this which we can call Recursive Partitioning. 45 00:03:06,10 --> 00:03:07,956 Lots and lots of recursive stuff in this class. 46 00:03:07,956 --> 00:03:10,863 The recursion is a little more conceptual, it's not like the Shannon 47 00:03:10,863 --> 00:03:14,127 co-factoring stuff, but you'll get the idea when we show you some pictures of 48 00:03:14,127 --> 00:03:17,810 the geometry. This is a bigger industrial example. 49 00:03:17,810 --> 00:03:19,418 I'm showing you this for a couple of reasons. 50 00:03:19,418 --> 00:03:24,150 One, just because it looks cool. This is something that was done by one of 51 00:03:24,150 --> 00:03:29,240 my students, Joan Shue. This benchmark is also from IBM. 52 00:03:29,240 --> 00:03:36,940 This has about 211,000 gates, they are in blue, and about 543 fixed blocks. 53 00:03:36,940 --> 00:03:39,746 Those are the red things. You imagine some designer has simply put 54 00:03:39,746 --> 00:03:43,320 them down in the right places where they want to go. 55 00:03:43,320 --> 00:03:46,904 And the image shows where the gates want to go if we modeled the blocks like big 56 00:03:46,904 --> 00:03:51,302 pads, if you think that. and this is a quadratic placement where 57 00:03:51,302 --> 00:03:54,998 we model all of the wires as two-point quadratic connections with appropriate 58 00:03:54,998 --> 00:03:59,33 fractional weights. And we solve the placement problem so 59 00:03:59,33 --> 00:04:03,660 there are pads around the outside, I'm just going to circle some pads. 60 00:04:03,660 --> 00:04:08,22 Those are all pads, all those little skinny boxes around the outside are pads. 61 00:04:08,22 --> 00:04:15,575 all of the 500 red boxes are either SRAMS or pads. 62 00:04:15,575 --> 00:04:23,165 That's all the stuff in red. and the blue smear is the result of the 2 63 00:04:23,165 --> 00:04:32,190 ax equals bx, ay equals by solved. So, why am I showing you this? 64 00:04:32,190 --> 00:04:34,980 this is an example of how badly imbalanced the quadratic placement can 65 00:04:34,980 --> 00:04:41,370 be. It can be terribly, terribly unphysical. 66 00:04:41,370 --> 00:04:44,580 So look, almost all the gates want to go up in the top left. 67 00:04:44,580 --> 00:04:47,691 That just says there's a lot of pads up there, and there's a lot of big dense 68 00:04:47,691 --> 00:04:50,853 wiring groups that go from the SRAMS and the top left to all of the gates that 69 00:04:50,853 --> 00:04:54,840 want to be there, but they can't go there. 70 00:04:54,840 --> 00:04:59,313 So, we're going to have to do something really smart to make the gates go into 71 00:04:59,313 --> 00:05:03,800 more physical, reasonable, realizable places. 72 00:05:03,800 --> 00:05:06,380 So, the big idea is this recursive partitioning. 73 00:05:06,380 --> 00:05:09,908 So, you do a first quadratic place, and I'm going to start calling quadratic 74 00:05:09,908 --> 00:05:13,778 places QPs, because it takes less space on my slides. 75 00:05:13,778 --> 00:05:17,447 And I'm going to write QP a lot. You do the first quadratic place and you 76 00:05:17,447 --> 00:05:21,924 get some weird blob of gates that minimizes the quadratic wire-length. 77 00:05:21,924 --> 00:05:26,620 Then, what you do is you partition the chip right in half. 78 00:05:26,620 --> 00:05:28,705 And so, I'm just going to draw a big line over here. 79 00:05:28,705 --> 00:05:33,60 You partition the chip in half, and you make a decision. 80 00:05:33,60 --> 00:05:35,726 Some of the gates are going to go on the left, some of the gates are going to go 81 00:05:35,726 --> 00:05:39,686 on the right. You formulate two new smaller quadratic 82 00:05:39,686 --> 00:05:44,348 placement problems where you say, the gates on the left must stay on the left 83 00:05:44,348 --> 00:05:49,650 and the gates on the right must stay on the right. 84 00:05:49,650 --> 00:05:53,115 And so, I'll solve two new quadratic placement problems that are each about 85 00:05:53,115 --> 00:05:58,101 half the size of the first one. And then, why this is recursive? 86 00:05:58,101 --> 00:06:00,750 I will repeat. I will again partition things. 87 00:06:00,750 --> 00:06:04,105 But I will partition the region on the left by drawing a line to the left and 88 00:06:04,105 --> 00:06:06,808 the right. And I will partition the region on the 89 00:06:06,808 --> 00:06:09,662 right. Similarly, by drawing a slice to the left 90 00:06:09,662 --> 00:06:12,842 and the right, and I will say that the gates on the top on the left have to go 91 00:06:12,842 --> 00:06:18,490 on the top, and the gates on the bottom on the left have to go on the bottom. 92 00:06:18,490 --> 00:06:24,790 And so, I now get four regions, each with about 1 4th of the total gates.. 93 00:06:24,790 --> 00:06:28,552 I will solve four new smaller quadratic placement problems, and I'll see where 94 00:06:28,552 --> 00:06:32,140 they go. And I will just continue to do this until 95 00:06:32,140 --> 00:06:38,324 I get a placement that looks a little bit more like a real physical placement. 96 00:06:38,324 --> 00:06:41,50 So, the one on the right I'm showing you here, and this is a real one, by the way. 97 00:06:41,50 --> 00:06:45,60 This is the result after 16 QP solves. And you can just keep going until the 98 00:06:45,60 --> 00:06:49,974 number of gates in each of these little cells, these little grid squares, is 99 00:06:49,974 --> 00:06:57,462 something manageable. So, here's a high level recipe for how 100 00:06:57,462 --> 00:07:03,180 recursive partitioning is going to work. These are the big steps. 101 00:07:03,180 --> 00:07:06,726 There's the partitioning step itself. How do you divide the chip into new 102 00:07:06,726 --> 00:07:12,238 smaller placement tasks on which we can run a smaller quadratic placement? 103 00:07:13,400 --> 00:07:18,410 The assignment task says, which gates should go into each new smaller region? 104 00:07:18,410 --> 00:07:22,762 So, we run quadratic placement on a region, then we partition the region into 105 00:07:22,762 --> 00:07:28,130 two smaller parts, and we assign gates to each of the two parts. 106 00:07:28,130 --> 00:07:32,30 Which gates go where? And there's the containment problem. 107 00:07:32,30 --> 00:07:35,930 How do you actually formulate the new quadratic placement matrix solve so the 108 00:07:35,930 --> 00:07:39,710 gates stay inside the new regions, but inside the new regions they go in good 109 00:07:39,710 --> 00:07:43,200 places. Because one of the problems is that, 110 00:07:43,200 --> 00:07:47,456 there are gates inside the region. The new region, the smaller region, that 111 00:07:47,456 --> 00:07:51,180 are connected to wires that go outside the region. 112 00:07:51,180 --> 00:07:54,456 How do we, how do we model that sort of connection from the inside of a smaller 113 00:07:54,456 --> 00:07:57,810 problem to the outside? That's the containment problem. 114 00:07:57,810 --> 00:08:01,780 And I'm going to talk about one early strategy from a classical paper. 115 00:08:01,780 --> 00:08:06,1 So, this is a paper from Ren Song Tsay, Ernie Kuh and Chi Ping Hsu called PROUD: 116 00:08:06,1 --> 00:08:11,380 A Sea-Of-Gates Placement Algorithm way back from December 1988. 117 00:08:11,380 --> 00:08:15,106 This is one of the first generation of analytical sort of placers, one of the 118 00:08:15,106 --> 00:08:19,982 first generation of quadratic placers. By modern standards, this is a very, very 119 00:08:19,982 --> 00:08:23,488 simple kind of a placer. Modern, modern placers are very much more 120 00:08:23,488 --> 00:08:25,682 complicated. The thing I like about the PROUD 121 00:08:25,682 --> 00:08:28,620 Algorithm, it's really easy to explain how it works. 122 00:08:28,620 --> 00:08:32,890 If you know how to do the basic quadratic placement mathematics it's not too hard 123 00:08:32,890 --> 00:08:36,611 to explain the partition step, the assignment step, and the containment 124 00:08:36,611 --> 00:08:40,194 step. They're all sort of fairly simple 125 00:08:40,194 --> 00:08:42,770 geometrically. It's a quite elegant solution, it's 126 00:08:42,770 --> 00:08:45,744 something you can actually, I think, get your head around. 127 00:08:45,744 --> 00:08:49,738 So, so let's talk about this. How does this recursive partitioning 128 00:08:49,738 --> 00:08:52,646 stuff work? Well, the, the first problem is, how do 129 00:08:52,646 --> 00:08:57,442 we actually do the partitioning? And the solution is that, after the first 130 00:08:57,442 --> 00:09:02,310 quadratic placement, we're going to divide the chip area exactly in half. 131 00:09:02,310 --> 00:09:05,650 And for us, we're just going to pick vertically as the way to divide it. 132 00:09:05,650 --> 00:09:08,110 Now note, this is completely arbitrary. You could divide it horizontally. 133 00:09:08,110 --> 00:09:10,993 But for us, it doesn't matter. We're just going to do a vertical 134 00:09:10,993 --> 00:09:15,706 division, and we want half of the gates on each side, right? 135 00:09:15,706 --> 00:09:20,122 So, we're going to slice it and we want half of the gates to be on the left-hand, 136 00:09:20,122 --> 00:09:25,555 and we want half of the gates to be on the right-hand side. 137 00:09:25,555 --> 00:09:29,160 And the question is, how do we make that happen? 138 00:09:29,160 --> 00:09:33,846 And why that could be a challenge is, and I'm showing you a little tiny picture of 139 00:09:33,846 --> 00:09:38,256 the IBM ASIC again. What if the quadratic placement does not 140 00:09:38,256 --> 00:09:40,990 spread the gates evenly between the halves? 141 00:09:40,990 --> 00:09:43,762 And so, I'm showing you my little cartoon of a chip that's a square with some pads 142 00:09:43,762 --> 00:09:48,200 around the edges, and there's, you know, about a dozen gates here. 143 00:09:48,200 --> 00:09:51,210 And they're all kind of smeared in the blob on the left. 144 00:09:51,210 --> 00:09:54,626 How do we know which gates to put on the left versus which gates to put on the 145 00:09:54,626 --> 00:09:58,322 right if this thing that I'm showing you is the initial quadratic placement, or 146 00:09:58,322 --> 00:10:02,74 set differently the quadratic placement is telling you they all want to go on the 147 00:10:02,74 --> 00:10:06,790 left? What the heck am I going to do? 148 00:10:06,790 --> 00:10:11,55 Well, that's just not acceptable, right? I have to do something that puts the 149 00:10:11,55 --> 00:10:17,223 gates in a sensible set of locations. So, what I'm going to do again[SOUND] is 150 00:10:17,223 --> 00:10:23,986 I'm going to partition the region that I'm placing exactly in the center. 151 00:10:23,986 --> 00:10:29,971 And I'm going to reformulate a new quadratic placement for the gates on each 152 00:10:29,971 --> 00:10:33,354 side. So my new problem is, how do I pick which 153 00:10:33,354 --> 00:10:36,89 are the right gates? This is the assignment problem. 154 00:10:37,360 --> 00:10:39,890 And the answer is actually lovely and simple. 155 00:10:39,890 --> 00:10:42,714 I've sort the gates. So, I sort the place gates first on their 156 00:10:42,714 --> 00:10:45,428 x-coordinate and then on their y-coordinate in the event that they are 157 00:10:45,428 --> 00:10:48,328 any ties. And honestly, if these things are based 158 00:10:48,328 --> 00:10:51,166 on floating point x's and floating point y's, you're probably not going to have 159 00:10:51,166 --> 00:10:54,490 too many ties. But you're going to do this anyway. 160 00:10:54,490 --> 00:10:56,783 First on x, and then if goes a tie, then on y. 161 00:10:57,870 --> 00:11:02,420 And so, the answer is that even if all of the gates are smeared in a clump way over 162 00:11:02,420 --> 00:11:06,620 on the left, when you sort it on x and then on y, you take the first N/2 gates 163 00:11:06,620 --> 00:11:13,440 in the sorted list, those are the ones that go on the left. 164 00:11:13,440 --> 00:11:17,516 All right, so that's those guys. Those guys go on the left, and all of the 165 00:11:17,516 --> 00:11:21,684 others go on the right. And you have now taken the initial 166 00:11:21,684 --> 00:11:25,560 quadratic placement and use the results of that placement, the x and 167 00:11:25,560 --> 00:11:29,890 y-coordinates, to do the assignment problem. 168 00:11:29,890 --> 00:11:34,26 Which gates go on the left? Answer, the half of them that are the 169 00:11:34,26 --> 00:11:38,146 most on the left. It sounds simple but, you know, it's what 170 00:11:38,146 --> 00:11:42,446 works. The leftmost half of the gates go on the 171 00:11:42,446 --> 00:11:48,890 left, the rightmost half of the gates go on the right. 172 00:11:48,890 --> 00:11:52,594 Now, we've got this thing that I'm, I'm calling the containment problem. 173 00:11:52,594 --> 00:11:55,550 So, you've now decided which gates go on the left. 174 00:11:55,550 --> 00:12:00,670 And so, I'm, I'm drawing the left part of the chip as a grey box. 175 00:12:00,670 --> 00:12:03,505 And I'm saying, let's focus on the gates inside this shaded region, R, on the 176 00:12:03,505 --> 00:12:07,235 left-hand side of the cut. I need to formulate a new quadratic 177 00:12:07,235 --> 00:12:11,330 placement problem to properly locate those gates in a region that's now the 178 00:12:11,330 --> 00:12:16,529 same height as the original QP problem, but half the width. 179 00:12:17,710 --> 00:12:20,895 And the new problem is, I want to solve a quadratic placement problem and I want 180 00:12:20,895 --> 00:12:24,130 all the gates to stay there on the left hand side. 181 00:12:24,130 --> 00:12:28,360 And I've really got two things that I've got to worry about. 182 00:12:28,360 --> 00:12:33,650 The first is, how do I keep the gates on the left-hand side on the left-hand side? 183 00:12:33,650 --> 00:12:39,380 How do I keep them in the gray box? And the second part is, how do I model 184 00:12:39,380 --> 00:12:43,540 the wires that connect from those gates on the left-hand side to the gates and 185 00:12:43,540 --> 00:12:50,158 pads on the right-hand side because, you know, I cannot ignore those things? 186 00:12:50,158 --> 00:12:53,986 You know, the reason that the quadratic placement problem is you know, is so 187 00:12:53,986 --> 00:12:57,640 attractive and why people like this method is that it optimizes the lengths 188 00:12:57,640 --> 00:13:02,505 of all the wires. If in the partitioning problem we ignore 189 00:13:02,505 --> 00:13:06,105 the fact that there are, say a whole bunch of wires that connect the gates 190 00:13:06,105 --> 00:13:09,945 that are not on the left-hand side, we're going to put those gates in the wrong 191 00:13:09,945 --> 00:13:14,451 place. You know, the gates that are heavily 192 00:13:14,451 --> 00:13:18,411 connected to the gates on the right-hand side, they probably be want to be on the 193 00:13:18,411 --> 00:13:23,800 right-hand side of the grey box. I can't just take all those wires and 194 00:13:23,800 --> 00:13:27,176 make them vanish, I have to do something with those. 195 00:13:27,176 --> 00:13:32,276 So again, there's a geometrically very attractive solution, and it's got a funny 196 00:13:32,276 --> 00:13:35,956 name. we're going to do something called 197 00:13:35,956 --> 00:13:39,800 Pseudo-pads. These are also called Pseudo-pins, 198 00:13:39,800 --> 00:13:46,125 sometimes. The basic idea is that every gate and pad 199 00:13:46,125 --> 00:13:54,260 not inside region R is modeled as a pad on the boundary of R. 200 00:13:54,260 --> 00:13:59,605 And the word that we use is propagate. We propagate these outside gates, or 201 00:13:59,605 --> 00:14:05,130 outside pads, using their current xy location to the nearest point on R, which 202 00:14:05,130 --> 00:14:10,308 is the grey box. And so, for this simple first cut we just 203 00:14:10,308 --> 00:14:14,194 take the y-coordinate and we put the pad on the center line, so that's the, that's 204 00:14:14,194 --> 00:14:19,605 the center line. So, you know, what actually happens here, 205 00:14:19,605 --> 00:14:23,97 right? Is that anything that the gate was 206 00:14:23,97 --> 00:14:28,720 connected to in R, that's connected on the right-hand side. 207 00:14:28,720 --> 00:14:32,564 So, imagine that there are a couple of gates which are the red circles, and a 208 00:14:32,564 --> 00:14:37,700 pad which is the red square. We take those things and we just slide 209 00:14:37,700 --> 00:14:44,410 them leftward and we pretend that they really live on the cut line, on the star. 210 00:14:44,410 --> 00:14:51,320 And so, we are not ignoring them. We're sort of doing the right thing. 211 00:14:51,320 --> 00:14:55,610 We are putting them in the right position on the boundary of region R so that when 212 00:14:55,610 --> 00:15:01,183 we replace all of these gates, right? When we do a new quadratic placement, 213 00:15:01,183 --> 00:15:04,976 there is some effect. You know, the gate on the top right is 214 00:15:04,976 --> 00:15:10,571 being pulled to a pad on the top right because that's where the real pad is. 215 00:15:10,571 --> 00:15:14,796 And the gates in the middle are being pulled to the rightward boundary because 216 00:15:14,796 --> 00:15:19,86 there are pads there that pretend to be like the gates that they are connected to 217 00:15:19,86 --> 00:15:25,666 only those pads aren't moving. So, this is what you get the resulting 218 00:15:25,666 --> 00:15:32,40 new quadratic placement problem for the gates in the left-hand region. 219 00:15:32,40 --> 00:15:37,132 And one of the reasons why this works so incredibly well is, remember the model of 220 00:15:37,132 --> 00:15:43,454 the wires as being like springs. If all of the pads are on the boundary of 221 00:15:43,454 --> 00:15:48,654 this new region, the gray region, and all of the wires are like springs, when we 222 00:15:48,654 --> 00:15:57,300 solve for the new gate locations, they're all going to stay inside the gray box. 223 00:15:57,300 --> 00:16:01,720 Because the springs between the wires between the gates pull the gates closer 224 00:16:01,720 --> 00:16:07,953 to each other, and the springs to the paths pull the gates close to the paths. 225 00:16:07,953 --> 00:16:12,532 But there is nothing that's going to pull the gate outside the box, right? 226 00:16:12,532 --> 00:16:16,558 So, by propagating the gates and paths outside the region to the boundary of the 227 00:16:16,558 --> 00:16:20,462 region, we get a quadratic placement problem that has the property that when 228 00:16:20,462 --> 00:16:26,859 we solve it, the gates will stay inside. And they will still respect the fact that 229 00:16:26,859 --> 00:16:30,458 the system stuff outside that's connecting to them and kind of pulling 230 00:16:30,458 --> 00:16:34,500 them to one part or another in the grey box. 231 00:16:34,500 --> 00:16:38,100 So, this is kind of the summary slide here. 232 00:16:38,100 --> 00:16:41,900 Why containment and propagation are so critical. 233 00:16:41,900 --> 00:16:46,322 On the left-hand side, the first point is you cannot ignore the gates outside the 234 00:16:46,322 --> 00:16:51,102 region that you're replacing. You want the gates inside the gray box on 235 00:16:51,102 --> 00:16:56,440 the left to feel some pull from the wires to the gates and pads outside the region. 236 00:16:56,440 --> 00:17:00,794 The pseudo-pads do this for us. So, there's all these blue wires, okay? 237 00:17:00,794 --> 00:17:05,279 there's all these blue wires here that are connected to things outside the gray 238 00:17:05,279 --> 00:17:09,199 region. The pseudo-pads pretend to be the gates 239 00:17:09,199 --> 00:17:14,248 ,and the paths that are not available to us to place anymore. 240 00:17:14,248 --> 00:17:18,260 So, the gates inside, they, they sort of go in the right place. 241 00:17:18,260 --> 00:17:22,414 And on the right-hand side, the pseudo-pads also guarantee containment, 242 00:17:22,414 --> 00:17:25,710 right? They guarantee that the gates locate 243 00:17:25,710 --> 00:17:29,576 inside the region. if you think of the pads as fixed things 244 00:17:29,576 --> 00:17:33,482 that the springs are connected to when the springs pull the gates toward the 245 00:17:33,482 --> 00:17:39,204 pads, they're never going to pull the gates outside the grey region. 246 00:17:39,204 --> 00:17:43,362 So, the pin propagation, pad propagation stuff does the right thing in terms of 247 00:17:43,362 --> 00:17:49,328 keeping a good global solution quality. It means you don't ignore the gates that 248 00:17:49,328 --> 00:17:53,24 are connected outside the gray region that you're replacing, and it means that 249 00:17:53,24 --> 00:17:57,491 containment is achieved. The gates stay inside the boxes as the 250 00:17:57,491 --> 00:18:01,658 boxes get smaller and smaller. So, this sounds maybe a little bit 251 00:18:01,658 --> 00:18:04,950 complicated. So obviously, the next thing is to do a 252 00:18:04,950 --> 00:18:15,342 little tiny example in a lot of detail. So, let's go do that next.