1 00:00:00,25 --> 00:00:08,213 [SOUND]. 2 00:00:08,213 --> 00:00:12,757 So here we are in lecture nine and as you know the title of the course is VLSI Cad 3 00:00:12,757 --> 00:00:17,619 Logic to Layout. So we had to get to layout eventually and 4 00:00:17,619 --> 00:00:21,905 here we are. So we've done lots of work in the boolean 5 00:00:21,905 --> 00:00:27,888 algebra logic hardware universe. We've done representation, we've done 6 00:00:27,888 --> 00:00:32,561 optimization, we've done synthesis. We sort of know how to make the gates. 7 00:00:32,561 --> 00:00:35,844 Right, what we have to do next is we have to figure out geometrically where they go 8 00:00:35,844 --> 00:00:39,55 and how we connect them. And so, we're going to move into the part 9 00:00:39,55 --> 00:00:41,120 of the course where we get to talk about layout. 10 00:00:41,120 --> 00:00:45,24 And we're going to start by talking about ASIC placement And so this is the 11 00:00:45,24 --> 00:00:49,120 question of, now that I have a million gates, where do they go on the surface of 12 00:00:49,120 --> 00:00:53,319 the chip? And so, what we're going to start with is 13 00:00:53,319 --> 00:00:56,360 a sort of an overview of just what's the terminology? 14 00:00:56,360 --> 00:00:59,150 What does the technology landscape look like? 15 00:00:59,150 --> 00:01:03,270 What do we have as the basic placeable elements? 16 00:01:03,270 --> 00:01:05,680 What's the technology components of this problem. 17 00:01:05,680 --> 00:01:08,112 And then we can start actually talking about some interesting new geometric 18 00:01:08,112 --> 00:01:10,856 algorithms. So, let's go look at the basics to get us 19 00:01:10,856 --> 00:01:15,570 started with ASIC placement. So, this is a little bit of review here. 20 00:01:15,570 --> 00:01:18,10 What do you know? I think you know a lot about 21 00:01:18,10 --> 00:01:20,999 computational boolean algebra at this point, I think you know a lot about 22 00:01:20,999 --> 00:01:24,710 representation You know a little bit of verification. 23 00:01:24,710 --> 00:01:27,797 You know a lot of things about synthesis and optimization for two-level and 24 00:01:27,797 --> 00:01:30,30 multilevel logic. This has a name. 25 00:01:30,30 --> 00:01:32,590 This is called the front end of the ASIC design process. 26 00:01:32,590 --> 00:01:35,370 So if you, you want to think of this at a very high level. 27 00:01:35,370 --> 00:01:38,832 Give a high level description. You know, something that comes in, in say 28 00:01:38,832 --> 00:01:42,216 VHDL or Verilog. There's some compiler like things that 29 00:01:42,216 --> 00:01:45,648 happen that, that turn that into a form that, to which we can actually apply, all 30 00:01:45,648 --> 00:01:50,340 of the synthesis and verification technologies that you now know. 31 00:01:50,340 --> 00:01:53,997 And what comes out of that is a connected set of gates and wires in the Technology 32 00:01:53,997 --> 00:01:57,283 associated with your chip, that has a name that's called a netlist, we'll, 33 00:01:57,283 --> 00:02:02,342 we'll revisit that in a minute. What you don't know is the next part of 34 00:02:02,342 --> 00:02:06,120 the ASIC design process, which is called the back end problem. 35 00:02:06,120 --> 00:02:12,48 Turning these IC's into masks to build real chips this is called layout. 36 00:02:12,48 --> 00:02:15,504 it's also called physical design, which is a named that is kind of a hold over 37 00:02:15,504 --> 00:02:19,904 from a very early[INAUDIBLE] . Days of the the electronic business when 38 00:02:19,904 --> 00:02:23,284 people were putting little you know, little packages on big boards in order to 39 00:02:23,284 --> 00:02:27,536 build any kind of electronic system. We're going to start with something 40 00:02:27,536 --> 00:02:30,140 called the placement problem, which is how do you locate those gates on the 41 00:02:30,140 --> 00:02:33,740 surface of a Of a piece of silicon. But, but to do that, 42 00:02:33,740 --> 00:02:39,636 I need to back up just a little bit. So, in honest fact, there's 1 missing key 43 00:02:39,636 --> 00:02:42,826 step. So, what comes out of multi level 44 00:02:42,826 --> 00:02:47,550 synthesis is not actually gates. it's a Boolean network model. 45 00:02:47,550 --> 00:02:50,254 It's a, it's a graph of nodes. Each of which is a, a 2 level sum of 46 00:02:50,254 --> 00:02:53,765 products form. as I'm showing here I'm actually picking 47 00:02:53,765 --> 00:02:57,718 one of the pictures from one of the assignments for this class and and just 48 00:02:57,718 --> 00:03:02,30 showing it here. What comes out of multi-level synthesis 49 00:03:02,30 --> 00:03:05,831 is actually not logic gates. We have to do something to turn it into 50 00:03:05,831 --> 00:03:08,680 logic gates. And there's a key step. 51 00:03:08,680 --> 00:03:10,530 And that step is called Technology Mapping. 52 00:03:10,530 --> 00:03:14,360 That transforms the abstract form of the above network. 53 00:03:14,360 --> 00:03:18,820 The result of multi-level logic synthesis into real logic gates and wires. 54 00:03:18,820 --> 00:03:22,20 I'm going to cover this next week and not this week because. 55 00:03:22,20 --> 00:03:25,760 We're actually going to do a programming assignment in this mook, that's a placer. 56 00:03:25,760 --> 00:03:29,300 And I need to just get you the, the methods and models and mathematics and 57 00:03:29,300 --> 00:03:33,300 algorithms of placement in order to let you do that. 58 00:03:33,300 --> 00:03:35,801 So we're doing this a little bit out of order, and I just want to explain why 59 00:03:35,801 --> 00:03:40,180 we're doing that. So, placement for ASICs. 60 00:03:40,180 --> 00:03:43,779 We're going to focus on the most common tasks in, in layout, and what we're 61 00:03:43,779 --> 00:03:49,194 going to focus on are layout tasks associated with row based standard cells. 62 00:03:49,194 --> 00:03:54,230 So, synthesis and mapping is going to give us a net list of gates and wires. 63 00:03:54,230 --> 00:03:57,392 Our job is to place them optimally in rows on regions of the chip and to route 64 00:03:57,392 --> 00:04:01,795 the wires that connect everything. So this is a chip I showed way back when 65 00:04:01,795 --> 00:04:05,700 at the very early, lecture. introduction to the class. 66 00:04:05,700 --> 00:04:10,311 And I'm just highlighting. Two two regions on this chip that are 67 00:04:10,311 --> 00:04:16,317 actually rows of standard cell logic. that's the job that we're going to do 68 00:04:16,317 --> 00:04:18,894 when we start looking at the layout problem. 69 00:04:18,894 --> 00:04:23,254 Now, what do you start with? You start with something called a 70 00:04:23,254 --> 00:04:26,938 standard cell library. And this is a slightly confusing name. 71 00:04:26,938 --> 00:04:30,900 So, just to very clear about this. This is a library. 72 00:04:30,900 --> 00:04:37,640 And the things that are in this library are themselves called standard cells. 73 00:04:37,640 --> 00:04:42,656 And a standard cell is a basic logic gate or a small logic element, that you get to 74 00:04:42,656 --> 00:04:47,352 use to create the substance of your design. 75 00:04:47,352 --> 00:04:50,667 So, the way to think of this is, this is the set of allowed logic elements you get 76 00:04:50,667 --> 00:04:53,982 to use to build your chip, so you get, for example, you know, inverters, and you 77 00:04:53,982 --> 00:04:57,450 get NAND gates with, let's say, you know, a couple of different numbers of inputs, 78 00:04:57,450 --> 00:05:00,714 and you get NOR gates, and you get some little tiny Useful things that are, are 79 00:05:00,714 --> 00:05:04,182 used all over the place like one bit ADDERs and two to one multiplexers, and 80 00:05:04,182 --> 00:05:11,830 so on. And you also get sequential elements 81 00:05:11,830 --> 00:05:18,430 things like d flip flops and registers. Why do we restrict ourselves to operating 82 00:05:18,430 --> 00:05:22,440 with these, if you will, predefined elements? 83 00:05:22,440 --> 00:05:25,656 And the answer is that there's lots of complicated electricity stuff going on at 84 00:05:25,656 --> 00:05:29,715 the transistor level. Each of these cells in our standard cell 85 00:05:29,715 --> 00:05:33,875 library hides all of this difficult electrical detail and presents a simple 86 00:05:33,875 --> 00:05:38,295 geometric abstraction that we can use for our geometry design algorithms to work 87 00:05:38,295 --> 00:05:42,968 with. So, an interesting question, how big is a 88 00:05:42,968 --> 00:05:46,902 standard cell library? how many cells are there in a cell 89 00:05:46,902 --> 00:05:49,180 library? And the interesting answer is they're 90 00:05:49,180 --> 00:05:51,531 often pretty big. you have to have all of the logic 91 00:05:51,531 --> 00:05:54,719 functions that you need. You have to have all of the input and 92 00:05:54,719 --> 00:05:57,430 output variants, in terms of how many pins. 93 00:05:57,430 --> 00:06:01,517 There are often several timing variants things that are fast but have higher 94 00:06:01,517 --> 00:06:05,839 power or slow and have lower power. Different sorts of electrical drive 95 00:06:05,839 --> 00:06:08,559 strengths, and so on. At a very high level the way to think 96 00:06:08,559 --> 00:06:11,492 about this is that there's a lot of different logic functions. 97 00:06:11,492 --> 00:06:16,120 So, you know, and and nand, or and nor, xor and xnor. 98 00:06:16,120 --> 00:06:19,332 Things like that. And a bunch of different kinds of flip 99 00:06:19,332 --> 00:06:21,532 flops. There's a lot of fan in and fan out 100 00:06:21,532 --> 00:06:24,706 variants, so you probably want NAND gates that have two inputs and three inputs and 101 00:06:24,706 --> 00:06:28,694 four inputs for example. Ditto for all the other kinds of basic 102 00:06:28,694 --> 00:06:31,98 logic gates. There's a lot of different timing 103 00:06:31,98 --> 00:06:33,606 variations. There's a lot of different kinds of flip 104 00:06:33,606 --> 00:06:36,263 flops. there are a lot of, if you understand 105 00:06:36,263 --> 00:06:41,10 anything about how Testability is done on a modern chip with scan chains. 106 00:06:41,10 --> 00:06:43,760 There are a lot of different scan variations on flip flops. 107 00:06:43,760 --> 00:06:45,450 And if you don't know what that means, don't worry about it. 108 00:06:45,450 --> 00:06:48,474 I'm just sort of mentioning it as to one of the things that adds variation to a 109 00:06:48,474 --> 00:06:51,715 cell library. And there's a lot of different electrical 110 00:06:51,715 --> 00:06:54,700 variants, let's say drive strength kinds of variants. 111 00:06:54,700 --> 00:06:57,648 You multiply all those things together, it's easy to have a library with 1,000 or 112 00:06:57,648 --> 00:07:00,750 more. Standard cells. 113 00:07:00,750 --> 00:07:03,251 How should we think about what's inside a standard cell? 114 00:07:03,251 --> 00:07:07,451 think of a standard cell as a, as a, as a geometric container for the circuits, the 115 00:07:07,451 --> 00:07:11,711 electrical circuits, the transistor-level circuits that you need to make the logic 116 00:07:11,711 --> 00:07:15,800 functions. So inside the cell, there's complex 117 00:07:15,800 --> 00:07:19,705 devices, you know, transistors and wires and things, complex geometric mask things 118 00:07:19,705 --> 00:07:23,5 happening right down at the, sort of the nanoscale surface of the, of the 119 00:07:23,5 --> 00:07:27,526 integrated circuit. Complicated electrical issues, but 120 00:07:27,526 --> 00:07:30,390 outside the standard cell, it's a box with pins. 121 00:07:30,390 --> 00:07:33,690 And that sounds you know, a little simple minded, but really in order for the 122 00:07:33,690 --> 00:07:36,590 geometry things that we need to be able to do to optimize at the level of 123 00:07:36,590 --> 00:07:42,320 millions and millions of standard cells and wires, we need a simple abstraction. 124 00:07:42,320 --> 00:07:45,199 And the abstraction that it's a box with pins is going to work for us. 125 00:07:47,150 --> 00:07:50,920 let's look at a few real standard cells. This is in an older technology. 126 00:07:50,920 --> 00:07:55,162 This is 130 nanometers CMOS. You know, where we are today you know, 127 00:07:55,162 --> 00:07:57,990 lots of things are at the 32 nanometer node. 128 00:07:57,990 --> 00:08:01,950 There are some things, you know, popping out at the 22 nanometer node now things 129 00:08:01,950 --> 00:08:06,360 at sort of 15 nanometer node are in, are in, are in research. 130 00:08:06,360 --> 00:08:10,82 So this is an, an older technology. these are some pictures of some things 131 00:08:10,82 --> 00:08:14,114 from a website, www.vlsitetechnology.org, that has a bunch of open-source cells, so 132 00:08:14,114 --> 00:08:18,484 if you want to actually look at Transistor level designs. 133 00:08:18,484 --> 00:08:19,850 And, and, you know? Geometry designs. 134 00:08:19,850 --> 00:08:23,228 It's just an interesting place to go. 2 things that I want you to take away 135 00:08:23,228 --> 00:08:26,420 from this. The first is, here's a first fact. 136 00:08:26,420 --> 00:08:29,208 They all have the same height. And the reason is that we want to be able 137 00:08:29,208 --> 00:08:32,172 to arrange them in rows. And when we arrange them in rows, we can 138 00:08:32,172 --> 00:08:35,80 snap them together, if you will. We can. 139 00:08:35,80 --> 00:08:39,301 Put the power grids down so that the, the vdd and the vss power connect, we can 140 00:08:39,301 --> 00:08:43,799 make all of this stuff work. The second geometric fact to be aware of 141 00:08:43,799 --> 00:08:46,972 is they have very different widths as I'm, I'm showing you here. 142 00:08:46,972 --> 00:08:51,717 So, the cell on the left hand side is a NAND2, that's a, that's just a two input 143 00:08:51,717 --> 00:08:56,973 NAND gate, and the cell on the right is and Edge-triggered, D Flip Flop, so it's, 144 00:08:56,973 --> 00:09:01,61 it's going to have, a D input, it's going to have a queue and a queue bar 145 00:09:01,61 --> 00:09:10,560 going out, it's going to have a clock. Right, going in the D Flip Flop is much, 146 00:09:10,560 --> 00:09:13,449 much bigger than the NAND. And the reason it's got a lot more 147 00:09:13,449 --> 00:09:15,550 transistors in it to be able to do what it does. 148 00:09:15,550 --> 00:09:18,580 So standard cells, they all have the same height. 149 00:09:18,580 --> 00:09:21,322 We snap them together in rows. And they have different widths because 150 00:09:21,322 --> 00:09:25,196 they have different circuit complexity. In a realistic context, what we are 151 00:09:25,196 --> 00:09:30,173 talking about is placing the insides of one block on a, on a big system on chip 152 00:09:30,173 --> 00:09:35,502 kind of design. So here's an actually a real SOC design 153 00:09:35,502 --> 00:09:38,622 courtesy of my My friend and colleague Larry Pileggi at Carnegie Mellon 154 00:09:38,622 --> 00:09:42,326 University, Big, system on chip designs, big SOCs are 155 00:09:42,326 --> 00:09:45,270 often designed hierarchically, which means you figure out how, what each of 156 00:09:45,270 --> 00:09:48,30 the blocks is supposed to be, and then you may have, you know, hundreds of 157 00:09:48,30 --> 00:09:52,680 blocks that get put together in an appropriate way. 158 00:09:52,680 --> 00:09:55,848 To make a big SOC, and what's being shown in this particular picture of an SOC 159 00:09:55,848 --> 00:09:58,968 that's in the middle of being designed is there's a lot of pins around the edges 160 00:09:58,968 --> 00:10:03,900 and those are all the little slice things with the little colors. 161 00:10:03,900 --> 00:10:07,930 And then there's a bunch of blocks inside the SOC and some of them have a colored 162 00:10:07,930 --> 00:10:12,202 boarder, but they're gray. Those things are actually big memories, 163 00:10:12,202 --> 00:10:14,650 and you don't get to play with their insides. 164 00:10:14,650 --> 00:10:17,40 They get generated by some other kinds of CAD tools. 165 00:10:17,40 --> 00:10:20,904 But the things that have blobs of primary color, those are actually blocks that are 166 00:10:20,904 --> 00:10:24,30 being placed. And the reason that there are sort of 167 00:10:24,30 --> 00:10:27,313 funny shapes of the colors is that we are actually tagging and color coding where 168 00:10:27,313 --> 00:10:31,40 the blocks came from in the original source. 169 00:10:31,40 --> 00:10:34,122 let's say the verilog or the VHDL, and we're seeing sort of where did the gates 170 00:10:34,122 --> 00:10:37,60 actually go when we're doing the layout task. 171 00:10:37,60 --> 00:10:40,651 For our purposes, you can pick one of those rectangles and say, how am I going 172 00:10:40,651 --> 00:10:44,299 to place the however many hundred thousand or you know, half a million or a 173 00:10:44,299 --> 00:10:49,840 million gates Associated with the insides of one of those blocks. 174 00:10:49,840 --> 00:10:52,790 How am I going to arrange them in rows in some optimal fashion? 175 00:10:52,790 --> 00:10:55,410 How am I going to place them in rows, and how am I going to route them? 176 00:10:55,410 --> 00:10:57,752 That's actually what we're going to look at. 177 00:10:57,752 --> 00:11:01,658 So, let's just talk for a little bit about the size distribution on standard 178 00:11:01,658 --> 00:11:05,240 cells. The big thing to note is that small cells 179 00:11:05,240 --> 00:11:09,100 dominate but there's lots of wide cells, too. 180 00:11:09,100 --> 00:11:11,620 So this is an old example, but a published example. 181 00:11:11,620 --> 00:11:15,210 It's about 206,000 gates from an IBM ASIC. 182 00:11:15,210 --> 00:11:19,530 It's actually part of an IBM processor, way back when, in the late 1990's. 183 00:11:19,530 --> 00:11:24,30 It's done by Jens Vygen Of the University of Bonne. 184 00:11:24,30 --> 00:11:28,810 And this would be, sort of, 1 small block today on a, on a big SOC. 185 00:11:28,810 --> 00:11:31,476 You know, a big SOC may be, you know, 20 million gates, 50 million gates, 100 186 00:11:31,476 --> 00:11:35,930 million gates, a really, really big one. And what I'm showing on this graph is 187 00:11:35,930 --> 00:11:39,830 that on the horizontal axis, we are showing, basically, the width of the 188 00:11:39,830 --> 00:11:43,558 cells. Right, and you can think of the width as 189 00:11:43,558 --> 00:11:48,710 being how many pins wide is the cell, as I showed on the previous example. 190 00:11:48,710 --> 00:11:52,988 And on the vertical axis we're showing the number of cells, and so there's about 191 00:11:52,988 --> 00:11:56,780 200,000 cells, 200,000 gates in this design. 192 00:11:56,780 --> 00:12:00,550 And what you're seeing is something is one cell wide, that's just some sort of a 193 00:12:00,550 --> 00:12:04,378 filler, but you know, you know how many cells are two pins wide, oh something 194 00:12:04,378 --> 00:12:08,322 like, you know, 27,000, three pins wide, maybe 27,000 Four, five, six pins wide, a 195 00:12:08,322 --> 00:12:11,918 few more than 20,000, seven pins wide, only 10,000, eight pins wide, again 196 00:12:11,918 --> 00:12:15,804 25,000, that's a nice round number, nine, ten, 11, 12, 13, 14 pins wide, you know, 197 00:12:15,804 --> 00:12:19,284 just a couple thousand, but then an interesting bump out around 17 and 18 198 00:12:19,284 --> 00:12:22,822 pins wide, you know, more than 10,000 cells, and then you know, down in the 199 00:12:22,822 --> 00:12:30,835 noise. The way you can sort of think of this is 200 00:12:30,835 --> 00:12:33,805 that most of the small gates dominate, you know, the things with the two, three, 201 00:12:33,805 --> 00:12:37,812 four inputs, that's mostly what the net list is made out of. 202 00:12:37,812 --> 00:12:42,362 and just as a concrete example you know, what is this bar over here with 27 or 203 00:12:42,362 --> 00:12:47,893 28,000 things that are two pins wide? and the answer is that you know, that's 204 00:12:47,893 --> 00:12:50,953 an inverter, right, because as a standard cell that's got one pin for the input and 205 00:12:50,953 --> 00:12:56,53 one pin for the output. And what's this peak out here with things 206 00:12:56,53 --> 00:13:00,732 that are 17 or 18 standard cell widths wide. 207 00:13:00,732 --> 00:13:04,124 Probably, that's a mix of things, like little registers with, maybe, 4 bits, 208 00:13:04,124 --> 00:13:08,350 maybe 8 bits depending on how it was how it was implemented. 209 00:13:08,350 --> 00:13:11,860 But that's also probably things like flip flops, you know, with a D input and a Q 210 00:13:11,860 --> 00:13:17,610 output in a clock. So, mostly small cells dominate. 211 00:13:17,610 --> 00:13:21,450 Very small cells, things like two input NANDs, two input NORs, one input, one 212 00:13:21,450 --> 00:13:25,290 output inverters, but there's also a lot of things like flip flops in a modern 213 00:13:25,290 --> 00:13:29,593 design. there's an interesting, sort of an aside 214 00:13:29,593 --> 00:13:32,474 that I just wanted to share with everybody. 215 00:13:32,474 --> 00:13:37,560 it's, it's sort of the way people use language to talk about chip size. 216 00:13:37,560 --> 00:13:41,620 So this is a strange question. How bit is a 100 million gate ASIC? 217 00:13:41,620 --> 00:13:45,420 And surprisingly, it is almost not 100 million gates. 218 00:13:45,420 --> 00:13:50,445 the numbers are usually referred to in one of two ways, and the most common is, 219 00:13:50,445 --> 00:13:56,86 let's say, equivalent small gates. So the idea is that because there are 220 00:13:56,86 --> 00:14:00,702 lots of things on the surface of the chip, little gates, big gates, 221 00:14:00,702 --> 00:14:04,537 Adders, flip flops, all kinds of other stuff,we sort of transform them into an 222 00:14:04,537 --> 00:14:08,350 equivalent number of let's say 2 input NAND gates. 223 00:14:08,350 --> 00:14:10,790 So if we, as I'm showing you in the middle of this picture so here's a two 224 00:14:10,790 --> 00:14:14,870 input NAND gate, so how big is that? Well that's like one input. 225 00:14:14,870 --> 00:14:18,461 And here's something called a AOI22, so its 22 input and, a two input OR and an 226 00:14:18,461 --> 00:14:22,920 inverter, that's an atomic gate in a lot of cmoss libraries. 227 00:14:22,920 --> 00:14:25,924 That's maybe four gates in size. And then I've got a picture of a one gate 228 00:14:25,924 --> 00:14:28,270 adder, how big is that? maybe six gates. 229 00:14:28,270 --> 00:14:30,834 And then I got a picture of a D flip flop, how big is that? 230 00:14:30,834 --> 00:14:35,66 maybe ten gates, maybe more. the idea is you take all of your real 231 00:14:35,66 --> 00:14:39,900 logic elements, the ones you get to use in your technology library. 232 00:14:39,900 --> 00:14:42,950 And you sort of replace them with an equivalent number of gates. 233 00:14:42,950 --> 00:14:45,530 And when someone says, how big is your design, you add up those numbers of 234 00:14:45,530 --> 00:14:49,74 2-input NANDs and you use that. So, there's two things that people might 235 00:14:49,74 --> 00:14:52,450 tell you when they tell you how many millions of gates in their ASIC. 236 00:14:52,450 --> 00:14:55,785 One of them is gates. This is usually an equivalent little NAND 237 00:14:55,785 --> 00:15:00,437 gates, so this is usually a big number. The other is a term you might not have 238 00:15:00,437 --> 00:15:04,772 heard before called instances. This is the number of things you really 239 00:15:04,772 --> 00:15:08,146 used in your library. This is the number of things you really 240 00:15:08,146 --> 00:15:11,800 placed, you know, the number of things you actually had to find space for and 241 00:15:11,800 --> 00:15:16,160 put wires to connect to on the surface of your chip. 242 00:15:16,160 --> 00:15:19,680 And the basic rule today is that the instances is basically the gates divided 243 00:15:19,680 --> 00:15:22,498 by 4 or 5. So, you know big round numbers, if 244 00:15:22,498 --> 00:15:25,204 someone tells you they have a hundred million gate ASIC, how many instances are 245 00:15:25,204 --> 00:15:28,0 there? Probably 20 million. 246 00:15:28,0 --> 00:15:31,300 Five is probably the best number to use today, and honestly, they might not even 247 00:15:31,300 --> 00:15:34,648 all be gates. people might be taking their very large 248 00:15:34,648 --> 00:15:37,976 static RAM, SRAM memories and other blocks and converting those into, an 249 00:15:37,976 --> 00:15:41,304 approximate equivalent number of gates in terms of their silicon area, so If 250 00:15:41,304 --> 00:15:44,840 someone tells you they have a 100 million gate ASIC, they probably don't actually 251 00:15:44,840 --> 00:15:51,176 have 100 million logic gates. They probably have a maximum of 20 252 00:15:51,176 --> 00:15:56,436 million, might be less. So, what's our first problem as we 253 00:15:56,436 --> 00:16:01,980 actually talk about layout in in our MOOC? 254 00:16:01,980 --> 00:16:05,280 Our first problem is placement, and I've got a nice little diagram here. 255 00:16:05,280 --> 00:16:06,943 Up at the top, there's a picture of a netlist. 256 00:16:06,943 --> 00:16:09,530 The netlist goes through a box that says placement. 257 00:16:09,530 --> 00:16:12,460 And that turns into a bunch of rows of little gates and standard cells. 258 00:16:12,460 --> 00:16:14,310 That goes into a box that's called routing. 259 00:16:14,310 --> 00:16:17,930 And suddenly, little wires appear that connect all the gates. 260 00:16:17,930 --> 00:16:20,944 What does a placer do? A placer starts with a netlist of gates 261 00:16:20,944 --> 00:16:25,230 and wires and the output is the exact location of each gate. 262 00:16:25,230 --> 00:16:29,380 You know, where does it go? And the goal of the placer is to be. 263 00:16:29,380 --> 00:16:33,28 Creating a placement that allows us to route, which is to say to connect all of 264 00:16:33,28 --> 00:16:37,65 the wires. That is the most fundamental plask...uh, 265 00:16:37,65 --> 00:16:42,316 the most fundamental task of the placer. Is this hard? 266 00:16:42,316 --> 00:16:46,526 Oh yes, very, very, hard. A bad placement could lead to an enormous 267 00:16:46,526 --> 00:16:49,368 amount of extra wire, and if you have more wire, your chip may need to be 268 00:16:49,368 --> 00:16:52,850 bigger in order to be able to fit those wires. 269 00:16:52,850 --> 00:16:55,900 And it's going to be slower because there's delay to get your signal through 270 00:16:55,900 --> 00:16:59,250 those wires, and there's going to be more power because taking voltages up and down 271 00:16:59,250 --> 00:17:03,700 on all those wires is actually you know, consuming energy. 272 00:17:03,700 --> 00:17:05,930 It's very bad. And if the placement is extremely bad, 273 00:17:05,930 --> 00:17:08,585 the next tool in the flow, which is called the router, might actually be 274 00:17:08,585 --> 00:17:11,330 unable to connect all the wires or to meet the timing requirements of your 275 00:17:11,330 --> 00:17:15,388 chip. So, placement is an extremely important 276 00:17:15,388 --> 00:17:17,800 task. Very critical task. 277 00:17:17,800 --> 00:17:20,744 Very critical for us to get right and so, it's the first task we're going to focus 278 00:17:20,744 --> 00:17:22,886 on. So, let's go talk about how we really do 279 00:17:22,886 --> 00:17:23,655 placement. 280 00:17:23,655 --> 00:17:29,757 [MUSIC]