1 00:00:00,012 --> 00:00:05,905 Hi and welcome to Module 7.3, which will wrap up the module on Quantization. 2 00:00:05,905 --> 00:00:10,718 So, in this module, we're going to look at what happens when we go back and forth 3 00:00:10,718 --> 00:00:13,813 from the analog to the digital world in practice. 4 00:00:13,814 --> 00:00:17,907 So, for instance, look at this box. This box is a high quality A to D and D to 5 00:00:17,907 --> 00:00:23,649 A, analog to digital and digital to analog converter, that I can use to record my 6 00:00:23,649 --> 00:00:26,970 bass or my guitar. Now, what's inside this box? 7 00:00:26,970 --> 00:00:31,443 How does this box work? And so, what we will do, is look at very 8 00:00:31,443 --> 00:00:36,755 simple circuits that illustrate how digital to analog and analog to digital 9 00:00:36,755 --> 00:00:40,292 converter work. Now, of course, we cannot go too deep into 10 00:00:40,292 --> 00:00:44,814 the description because this is not an electronics class, but even the simple 11 00:00:44,814 --> 00:00:48,390 overview will give you a pretty good idea of how things work. 12 00:00:48,390 --> 00:00:50,285 And you will see that it's not too complicated. 13 00:00:50,286 --> 00:00:55,890 Hi and welcome to Module 7.3 of Digital Signal Processing. 14 00:00:55,890 --> 00:00:59,850 In this module we will talk about analog to digital and digital to analog 15 00:00:59,850 --> 00:01:02,663 conversion. Try to understand how these things are 16 00:01:02,663 --> 00:01:05,673 done in practice. We have seen that sampling discretizes 17 00:01:05,673 --> 00:01:08,139 time and quantization discretizes amplitude. 18 00:01:08,139 --> 00:01:14,275 But how is it done in, In practice? The answer is cheaply and in a very 19 00:01:14,275 --> 00:01:17,788 compact way. This photograph shows you the few discrete 20 00:01:17,788 --> 00:01:22,072 electronic components that you have to put together to build an analog to digital 21 00:01:22,072 --> 00:01:25,524 converter. And if you did so, you would probably end 22 00:01:25,524 --> 00:01:30,012 up with one of the largest digital to analog converters in existence because in 23 00:01:30,012 --> 00:01:34,432 most cases, like in your cell phone, the whole circuit would be integrated and 24 00:01:34,432 --> 00:01:37,748 miniaturized. At the heart of both digital to analog and 25 00:01:37,748 --> 00:01:42,860 analog to digital converters is a circuit called the operational amplifier or op-amp 26 00:01:42,860 --> 00:01:45,870 for short. The op-amp has two inputs, the inverting 27 00:01:45,870 --> 00:01:48,785 input and the non inverting input, and one output. 28 00:01:48,785 --> 00:01:55,926 And the input-output relationship is that the voltage, at the output is equal to the 29 00:01:55,926 --> 00:02:02,964 difference between the voltages at the inverting and non inverting input, times a 30 00:02:02,964 --> 00:02:06,812 gain factor. We idealize the op-amp by saying that it 31 00:02:06,812 --> 00:02:10,064 has infinite input gain and zero input current. 32 00:02:10,064 --> 00:02:15,089 And although these are, of course, idealizations, practical implementations 33 00:02:15,089 --> 00:02:19,182 of operational amplifiers are remarkably close to this ideal. 34 00:02:19,182 --> 00:02:23,819 And not very complex either, because this, for instance, is the schematics for an 35 00:02:23,819 --> 00:02:28,579 operational amplifier and you can see that it only requires six transistors and one 36 00:02:28,579 --> 00:02:31,458 resistor. The operational amplifier can be used in 37 00:02:31,458 --> 00:02:34,153 two configurations, the open loop and closed loop. 38 00:02:34,154 --> 00:02:37,889 In the open loop configuration, the op-amp works as a comparator. 39 00:02:37,890 --> 00:02:42,966 You put a reference voltage at the inverting input and a test voltage at the 40 00:02:42,966 --> 00:02:47,352 non-inverting input. As soon as the difference between these 2 41 00:02:47,352 --> 00:02:52,913 voltages is non-zero, the output due to the infinite gain will shoot up or down to 42 00:02:52,913 --> 00:02:58,557 the maximum or minimum allowed output voltage, which coincides with the voltage 43 00:02:58,557 --> 00:03:01,607 of the power supply that powers the op-amp. 44 00:03:01,608 --> 00:03:06,992 In the closed loop configuration, we have a feedback path that links the output to 45 00:03:06,992 --> 00:03:11,064 the inverting input. So, what happens when we apply a voltage 46 00:03:11,064 --> 00:03:15,244 to the non-invertant input? Well, if the voltage at the inverting 47 00:03:15,244 --> 00:03:20,498 input is less than x, then the difference between inverting and non-inverting would 48 00:03:20,498 --> 00:03:24,510 drive the output up. Conversely, if the voltage here was larger 49 00:03:24,510 --> 00:03:29,517 than x, the difference would be negative and this would drive the output down. 50 00:03:29,518 --> 00:03:34,030 So, the only equilibrium point for this system is when the voltage at the 51 00:03:34,030 --> 00:03:38,980 inverting input is exactly equal to x, which of course means the output voltage 52 00:03:38,980 --> 00:03:42,806 is equal to x as well. So, the input-output relationship of the 53 00:03:42,806 --> 00:03:48,035 closed loop is output equal to the input. This configuration is known as a buffer 54 00:03:48,035 --> 00:03:52,950 stage because although the output has the same voltage as the input. 55 00:03:52,950 --> 00:03:58,401 The second property of the ideal op-amp prevents any current from flowing into the 56 00:03:58,401 --> 00:04:02,398 amplifier. Therefore there is a separation between 57 00:04:02,398 --> 00:04:07,315 this side and that side of the amplifier. This is very useful for taking 58 00:04:07,315 --> 00:04:10,777 measurements without perturbing the measured quantity. 59 00:04:10,778 --> 00:04:15,040 We can complexify the closed loop a little bit by adding a couple of resistors. 60 00:04:15,040 --> 00:04:19,062 In this case, we have what is called an inverting amplifier. 61 00:04:19,062 --> 00:04:23,616 This is always likely more complex than the simple closed loop we saw before. 62 00:04:23,616 --> 00:04:28,102 Again, the system will stabilize when the difference between inverting and 63 00:04:28,102 --> 00:04:32,810 non-inverting inputs is zero. So, we can say that the voltage here, 64 00:04:32,810 --> 00:04:38,262 let's call it V0, is equal to zero, because the non-inverting input is 65 00:04:38,262 --> 00:04:44,104 connected to ground. That means that the current flow in, in 66 00:04:44,104 --> 00:04:51,922 the first resistor will be according to Ohm's Law i0 equal to x over R1. 67 00:04:51,922 --> 00:04:56,760 This current will not be able to flow into the operational amplifier because of the 68 00:04:56,760 --> 00:04:59,284 second law. So, we'll have to flow into this resistor 69 00:04:59,284 --> 00:05:03,820 here. And therefore, the output voltage will be 70 00:05:03,820 --> 00:05:08,192 just the voltage drop over R2, caused by i0. 71 00:05:08,192 --> 00:05:14,361 And so y is equal to minus R2 over i0, which gives us the final input-output 72 00:05:14,361 --> 00:05:20,588 relationship for the inverting amplifier. The output is a fraction of the input, 73 00:05:20,588 --> 00:05:24,116 with a change of sign. We're now ready to look at an A to D 74 00:05:24,116 --> 00:05:27,795 converter. The device starts with a sample and hold 75 00:05:27,795 --> 00:05:32,259 circuit that performs the sampling. So we have our analog input here. 76 00:05:32,259 --> 00:05:35,709 Here we have an op-amp in buffer configuration. 77 00:05:35,709 --> 00:05:39,820 And here we have a MOSFET which is really like a switch. 78 00:05:39,821 --> 00:05:43,300 And here we have a train of pulses at the sampling frequency. 79 00:05:43,300 --> 00:05:48,890 When a pulse reaches the gate at the MOSFET, the MOSFET closes very briefly and 80 00:05:48,890 --> 00:05:54,566 allows the first buffer to charge this capacitor to the instantaneous level of 81 00:05:54,566 --> 00:05:58,592 the input signal. The capacitor is connected to another 82 00:05:58,592 --> 00:06:04,262 buffer stage that will put out the volume measured by the capacitor for the duration 83 00:06:04,262 --> 00:06:09,304 of the interval between pulses. We put a buffer stage here so that we can 84 00:06:09,304 --> 00:06:15,046 put out a constant voltage without discharging the capacitor, between sample 85 00:06:15,046 --> 00:06:18,638 in instance. An analog to digital converter needs not 86 00:06:18,638 --> 00:06:22,273 only to sample the input signal, but also to quantize it. 87 00:06:22,273 --> 00:06:27,788 So, the sample and hold provides a stable voltage level between sample and times, 88 00:06:27,788 --> 00:06:32,000 and now we need a circuit that converts that to binary format. 89 00:06:32,000 --> 00:06:34,728 Here we have a simple diagram of a two-bit quantizer. 90 00:06:34,728 --> 00:06:40,915 What this quantizer does is take a maximum positive voltage, V0, and a minimum 91 00:06:40,915 --> 00:06:46,268 negative voltage minus V0. This could be the A and B extrema that we 92 00:06:46,268 --> 00:06:52,472 used in our quantization example. And then, uses a series of four resistors 93 00:06:52,472 --> 00:06:57,243 of equal value to produce intermediate boundary levels. 94 00:06:57,244 --> 00:07:03,300 The iK's in our quantization example that will be used to define the quantization 95 00:07:03,300 --> 00:07:05,771 regions. Here, you have plus 0.5 Volts. 96 00:07:05,771 --> 00:07:09,140 Here, you have zero Volts. Here, you have minus 0.5 Volts. 97 00:07:09,140 --> 00:07:16,637 So, we're dividing the interval from V0 to minus V0 into four equally spaced 98 00:07:16,637 --> 00:07:21,061 intervals. These reference voltages here are used 99 00:07:21,061 --> 00:07:27,657 with a bank of comparators so, operational amplifiers in open loop, to determine 100 00:07:27,657 --> 00:07:33,127 which quantization interval the current sample value belongs to. 101 00:07:33,128 --> 00:07:40,242 So, let's work out an example with an input voltage of 0.2 V0. 102 00:07:40,243 --> 00:07:44,683 So, what have here is that the first comparator will have 0.2 Volts at the 103 00:07:44,683 --> 00:07:48,073 non-inverting input with the reference of 0.5 Volts. 104 00:07:48,073 --> 00:07:52,374 So, the reference is higher. So, here the output will be a negative 105 00:07:52,374 --> 00:07:56,315 voltage. This comparator will compare 0.2 Volts to 106 00:07:56,315 --> 00:08:00,163 0 Volts. And so, this comparator will output a 107 00:08:00,163 --> 00:08:06,262 positive voltage and similarly this one will compare 0.2 to minus 0.5. 108 00:08:06,262 --> 00:08:12,432 So, again the output will be positive. Next, we have a logic network that will 109 00:08:12,432 --> 00:08:16,345 encode this comparison levels into a binary value. 110 00:08:16,345 --> 00:08:23,861 These are Exclusive OR gates and the truth table for this gates Is the following. 111 00:08:23,862 --> 00:08:30,670 So, the output will be positive only if the inputs are of different sign. 112 00:08:30,670 --> 00:08:37,040 So, this gate will output a positive level and this gate will output a negative 113 00:08:37,040 --> 00:08:40,831 level. Now, we have a network of diodes that acts 114 00:08:40,831 --> 00:08:45,027 as a parallel to serial converter. So, we have a negative voltage here that 115 00:08:45,027 --> 00:08:48,366 will be blocked by these two diodes so nothing happens here. 116 00:08:48,367 --> 00:08:52,879 A positive voltage here that will go through, and will indicate the most 117 00:08:52,879 --> 00:08:56,983 significant bit out of the quantizer. Since this is positive, the most 118 00:08:56,983 --> 00:09:00,818 significant bit will be one. And here, the negative voltage will not go 119 00:09:00,818 --> 00:09:05,438 through the diode so the least significant bit will be connected to the ground and it 120 00:09:05,438 --> 00:09:11,525 will be equal to zero. So, the voltage of 0.2 V0 will be encoded 121 00:09:11,525 --> 00:09:17,380 by the binary notation 1 0. Finally, let's look at a D to A converter. 122 00:09:17,380 --> 00:09:26,602 Suppose we have a sample in binary notation, so x of n is equal to a set of 123 00:09:26,602 --> 00:09:34,269 bits from zero, b1 to bR minus 1, so we use R bits per sample. 124 00:09:35,270 --> 00:09:42,308 We use this binary representation to drive a bank of voltage generators at voltage 125 00:09:42,308 --> 00:09:45,780 V0. So, in the previous example, we had a 2 126 00:09:45,780 --> 00:09:51,580 bit quantizer that gave us a representation for our current value of 1 127 00:09:51,580 --> 00:09:54,292 0. So, in that case, if we were to apply that 128 00:09:54,292 --> 00:09:59,176 value to this backup of generators, this voltage generator would be on and this 129 00:09:59,176 --> 00:10:04,274 voltage generator would be off. These generator are connected to a 130 00:10:04,274 --> 00:10:09,950 resistors structure that is known under the name of R2R ladder. 131 00:10:09,950 --> 00:10:15,634 Now the details of this structure are a little bit tedious to work out. 132 00:10:15,635 --> 00:10:22,584 But if you're patient and you apply Thevenin's Theorem to this ladder, you 133 00:10:22,584 --> 00:10:29,325 will see that the system seen by this point in the circuit, is equivalent to a 134 00:10:29,325 --> 00:10:36,066 resistor of value R, connected to a voltage source of value V equal to the sum 135 00:10:36,066 --> 00:10:42,773 for K that goes from zero to R minus one of V0 divided by two to the K times bK. 136 00:10:42,773 --> 00:10:51,029 So, in other words, each bit in the minor representation of the sample contributes a 137 00:10:51,029 --> 00:10:58,487 voltage source of value V0 over 2K where K is the position of the bit in the binary 138 00:10:58,487 --> 00:11:04,643 representation. So, if this is equivalent to a voltage 139 00:11:04,643 --> 00:11:13,447 source of value K, V0 over 2K b0, plus a resistor of value R, this is simply an 140 00:11:13,447 --> 00:11:22,961 inverting amplifier and the value out here will be minus V0 times x, where x is our 141 00:11:22,961 --> 00:11:31,140 binary representation of the input. The resulting signal will be a piecewise 142 00:11:31,140 --> 00:11:38,095 constant signal where the transitions between levels will be dictated by the 143 00:11:38,095 --> 00:11:43,684 speed which new samples appear at the voltage generator bank.