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Let's, let's look at a baseline 2-way
in-order superscalar.

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That's a mouthful to say.
So, difference than the pipelines you've

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seen before.
We have two ALU's.

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It's a big difference.
We can execute two integer ops at the same

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time in this pipe.
Drawn here, we are going to actually

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differentiate these two pipes.
We are going to call this pipeline A and

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this pipeline B, and pipeline A lets say,
can do integer ops and branches, and

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pipeline B can do integer ops and memory
access.

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But you can't, you can't do memory up here
and you can't do branches down there.

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That's, there's nothing fundamental.
We're just going to look at it to sort of,

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basic example here, we have two asymmetric
pipelines.

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An important, important point of this,
first is that, compared to our 5-stage you

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know MIPS processor is that with will it
fetch two instructions at the same time.

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If we want to actually be able to execute
two things, we need to able somehow get

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that out of the instruction cache or the
instruction memory.

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Hm, okay.
Well, that's interesting.

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So, the program counter kind of sort of go
in here and instead of being one

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instruction now we actually get two to go
in these two different instruction

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registers.
We also need to add more ports to our

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register file.
Instead of, in our basic pipeline that we

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have talked about earlier, we had only two
read ports.

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You gave two different addresses and it
outputted two registers.

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Now, because we have two different
instructions at the same time, we actually

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have to pull out four different read ports
or four different read registers at the

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same time.
And, if we want to be able to retire or,

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commit instructions two at a time, we need
to add more write ports.

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So I, I show the register file here sort
of split into two.

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But, the register files kind of, it, it's
together, but logically I just drew it

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apart so, that you can actually make heads
or tails of the drawing.

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So that's, that's something interesting to
think about is, you have to, to worry

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about that.
Okay, so the first question I have here,

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is this good enough?
Is this pipeline diagram good enough in,

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let's say, the fetch stage?
We stick some addresses in, we get two

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instructions out.
So, that's a good question.

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Do we do PC and PC + four?
So, let's say we can, there's some logic

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which we pull out PC and PC + four at the
same time.

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So, we're executing two instructions.
So, so roughly, you know, we need to worry

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about alignment issues here.
We need to worry about branches is, let's

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say, the first instruction in, that we
pull out of the two instructions.

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In this next part here, Our pipes are not
symmetric.

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So, is this, is this good enough?
So, what happens if the first instruction

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that comes out here is a load.
So, instruction IR0 here.

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The instruction register just loaded with
the bits from the load.

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What, what happens down the stream here?
Can the load happen here?

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[inaudible].
Yeah.

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That's a problem.
So, we're starting to go with the

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superscalar here.
We need to start thinking about having,

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let's look back and forth here and take a
look at this.

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You need something here that can take an
instruction that will show up here and

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route all the operand values down over
here.

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Largely, a lot of times people call this
issue logic or instruction steering logic.

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So, you have to sort of steer the operands
and you're going to, you can basically

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swap the two operands, the two
instructions that are going down the pipe

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at the same time.
Okay, so, so that's, that's interesting,

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and this is, could actually cost some time
to do this.

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So, this might motivate us to have longer
pipelines.

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So, we'll talk about that in a second.
Another thing you have to do, is on the

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control side, is you have to actually
start thinking about duplicating control.

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So here, we actually have two decoders
because we're decoding two instructions at

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the same time.
So, the instruction register wires up to

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Decode A and this instruction register
wires up to Decode B and then they're

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going to drive singles down across the
respective A and B data paths.

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So, that's, something not drawn here, is
you may also, if you have to interchange

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these sort of instruction register zero to
the B pipe.

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You might have to, you definitely have
some, you know, communication or some,

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swapping of the instruction inputs here.
So that's, that's, that's sort of the

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baseline, 2-way processor.