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Now, we actually start to talk into do
things and how to build superscalar

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processors, things that exploit ILP,
sectional parallelism, things that run at

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really high clock frequency or multiple
cores and advanced techniques.

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So, before we start talking about
superscalar, there's a piece of

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nomenclature we need to introduce that
sort of goes hand in hand with the data

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hazard talk that we had before.
But, I didn't introduce it there, I need

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to introduce it now before we go into
actual superscalars.

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So, let's consider some example
instructions here where register i,

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register j, you operate r when you put it
into register k.

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And, we're going to look at different
types of dependencies, and we are going to

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name them.
So, the basic dependency here is a read

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after write hazard, or read after write
dependency.

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So, in this example here, and if, if time
goes down, this operation here is going to

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store into register three.
And then, this instruction here is going

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to read from r3.
So, you need to sort of, temporally make

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sure this happens before that because you
need the value here.

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Okay.
So, we, this is, we talked about this in

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our data hazards.
This is the most classic data hazard here,

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a read after write hazard.
Let's look at something a little bit more

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a little bit less intuitive.
Let's look at a hazard where this

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instruction here reads register one, and
the next instruction writes register one.

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Okay, that should be no problem.
That sounds great.

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Well, today, we're going to give an
example of a pipeline where this is a

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problem, or could potentially be a
problem.

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So, you know, if you do everything in
order and your instructions are sort of

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slowly flowing down the pipe and you're
only executing one instruction at a time,

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you're going to execute this, and then
that, and you're going to read register

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one here.
And then, like, a whole lot of time later

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you are going to write register one so
nothing, nothing bad happens.

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But, if you start to execute instructions
out of order, or if you start to execute

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multiple instructions at the same time,
you're going to start to come into some

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problems.
We're going to name this a write after

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read hazard.
So, what that means is, we have a write

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that temporally in the program order is
happening after a read of that same

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register.
So, when we, and this is usually called a

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antidependence.
And we need to, we need to maintain these

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when we go to execute our programs out of
order and sort of throw everything into a

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big bucket and try to pull out
instructions.

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Okay, output dependencies.
This is actually something that you could

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possible even think of having happen on a
simple sort of, in order processor core.

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If you do right back to the register file
from different stages.

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So, let's take an example if you have a
multiplier like in your lab which is going

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to write at the end of the pipe and have a
very, very high leniency and then you have

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a instruction like an add which is let's
say, you try to write to the register file

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early, you might actually write this
instructions result to register three

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before that instructions results.
If, let's say, this instruction here is a

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long leniency operation, so it could be
like a multiply, and this is like an add.

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So, we're going to call that a write after
write dependency.

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And we need to maintain the order here
that this gets written first, and then

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this gets written.
Because if you flop those two results or,

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or interchange those two results, the next
thing it goes to read r3, it can get the

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wrong value.
So, that's, that's pretty important.

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That's called an output dependence.
Okay.

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So, so last question, is there such a
thing as a read after read dependence or a

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read after read hazard?
So, superscalar processors.

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So far we've been limited to processors
that can only get a clock per instruction

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greater than or equal to one.
Superscalar processors will allow you to

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execute multiple instructions at the same
time and will move us into a new class

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here of the clock per instruction,
potentially below one.

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It's at least fundamentally possible.
Now, there might be other things that

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cause our clock per instruction to still
be above one, but we can get a higher

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performance by executing multiple
instructions in parallel.

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I want to introduce nomenclature here,
that's the reciprocal of instructions per,

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or clock per instruction, which is
instructions per clock.

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We just, we move them and rename it.
Sometimes people say IPC as the reciprocal

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of CPI versus CPI, clocks per instruction
equals one over instructions per clock.

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So, just, just be aware of that sometimes
we'll be using those terms different

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iInterchangeably in this class.
Okay.

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So, what types of superscalar processors
can we talk about?

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There's lots of different types.
There's in order machines and out of order

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machines, roughly.
And, what in order machine means is the

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machine or the, the processor is still
trying to execute instructions in program

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order.
Well, you don't have to do that.

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You could actually think about sort of
taking apart the program and executing

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them out of order as long as you're trying
to sort of, preserve the different

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hazards, data hazards.
And, something like your Pentium

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processor.
So, I'm going to pass around here a

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roughly Pentium [inaudible] class
processor.

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It's actually Intel Celeron Pentium,
Pentium [inaudible] version of the Intel

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Pentium Celeron, is a out of order, three
wide superscalar.

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So, it can execute three instructions at a
time.

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For instance, the, another example is the
original Pentium, the old Pentium when the

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original Pentium came out, that was a two
wide machine.

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So, it could execute two instructions at
one time and was in order.

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So, you can think about these different,
different notions.