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Let's start off our third topic so far in
our review of computer architecture.

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So this is, still review at this point.
As I said at the beginning of, of this

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class, if you know everything up to this
point in the class, that's a requisite or

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a prerequisite for this course.
We're just going to blow through

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everything you should know in order to
start the much more detailed, content

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later in the cour-, this course.
We talk about real processors you're gonna

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be building.
So things like out of order, multi issue,

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multi core, microprocessors versus simple
little processors you should have built in

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previous classes.
So, this is ELE 475 at Princeton

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University.
We're talking about computer architecture,

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and today we're going to be reviewing
caches.

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And this is the last topic cache review as
I said before we move on to a new material

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and the new material we're gonna be moving
onto very soon is superscalars or

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processors which can execute multiple
instructions per cycle.

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So let's take a look at the agenda for the
cash review lecture.

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We're going to start off by talking about
memory technology and motivate the

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different.
Or see we start off talking about memory

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technology and use that as a motivation
for caches.

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So we're gonna look at different types of
technology, DRAM versus SRAM, what the

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transistor technologies are behind them
versus or, or why we have these different

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memory technologies?
Why don't we just have one?

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What are there different ways to store
information?

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Why, why don't we just use register files
for everything?

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Or simple flip-flops for everything?
Then we're gonna motivate cache design or

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why we have caches?
So let's define what a cache is, a cache

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is a little piece of memory that you stick
next to something which does not have all

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of the information that you're trying to
store.

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Instead it has a subset of information and
hopefully it has a useful subset of that

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information.
We're then going to talk about

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classification of these different caches.
So we'll put names and labels on sort of

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different cache architectures.
So we're gonna talk about associativity of

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caches, we're gonna talk about size of
caches, we're gonna talk about whether the

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cache has multiple things that could fit
in one set or not.

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And we'll talk a bunch more about that.
And then we'll have a very, very brief

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introduction to cache performance or some
of the things we should know about why

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cache is going to give you good
performance right now.

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Later in this course, we're gonna actually
have two more lectures about advanced

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caches.
Advanced caches, we're gonna talk about,

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more sophisticated topics with, how do you
build an implement actual caches for very

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high performance processors?
So let's start talking about memory

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technology.
Okay.

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So, so let's, let's look at a, a memory.
Or something that can store multiple

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values, and give it back some data.
So here we have a very naive, flip flop

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based, register file.
You'd probably never actually build this

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in a modern micro processor.
But, let's, let's look at that sort of

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conceptual idea here of what, what a
memory really is.

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Here we have four entries, that are flip
flops.

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Maybe its multi bit wide?
So its maybe, I don't know, lets say

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these, each of these registers are 32 bits
wide and each of these buses is 32 bits

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wide.
And we're gonna sort of select, based on a

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readdress some value.
So we can choose, you know, this is two

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bits here, we can choose one of four
places.

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We have right data that comes in and we
just sort of broadcast that to all of the

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registers.
And we write depending on the right

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address here and the clock.
And, you know, if the decoder tells us to

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light this up and the clock clocks the
actual element, it will load in the value.

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You may even have a write enable on
something like this where that would also

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feed, let's say, into the end dates here.
So it'll say, if it writes not occurring,

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don't actually load anything into these
registers.

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Okay, so that's really, really naive.
Let's take something a little bit more

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complex and how these things sort of start
to actually, actually look.

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Okay, so now we're gonna transition from
talking about this naive register file and

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see what people actually built.
And, the first thing you should realize

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is, if you go to build something that's
naive register file you have lots and lots

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of bits as you add more and more bits
here.

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Here we only have four, but if we go to a
thousand bit register file this

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multiplexer goes really big and if you
stack these all up a thousand long your

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aspect ratio your x versus y or the size
when you go to lay it down on a piece of

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silicon is, is very long and very narrow.
So you will end up let's say with a 1000

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bits, one bit tall.
And that does not lay out very well, and

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it's not necessarily good for speed or
from a area perspective.

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So why is it not good for speed?
Well, it's not good for speed because

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wire, wires have cost and take time to
propagate.

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So you have to propagate from 1000 bits
away or 1000, bit cells away, all the way

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over to the multiplexer.
Your cycle time is not gonna be very fast

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versus if you would somehow make it more
square or more rectangular, the distances

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actually are minimized.
So this is how we end up with a rays or

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memory rays.
And we're going to look at a memory array

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for register file first.
Let's look at a register file array, and

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how you could possible actually go build
this, because it's a little bit different.

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We're not going to use fully complimentary
logic here for everything.

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Instead we are going to start to
transition to something where we will have

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more of analog circuits connecting our
bits to respective buses.

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And, we're also going to change how we do
the decode.

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We're not gonna have a full multiplexer
here, or a full decoder here.

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We're going to, split that into different
portions.

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So here we have an example array.
It's a square and we, each of these little

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boxes is a single storage element, bit
cell.

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And the address comes in here and that
goes up into a row decoder, which will

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turn on one of these wires at a time, and
these are called word lines.

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And we'll have both read word lines and
write word lines.

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This is still just for register file.
But we're actually gonna split out some of

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the bits here of our address and send it
over to here, which is the column decoder.

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And that's going to choose, this is, this
column decoder is just a multiplexer, very

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similar to this multiplexer.
But it's gonna only have a subset of the

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bits.
Instead of having all of the bits that are

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together here going through this, this
multiplexer and having N bit address

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coming into it, instead has a, a subset of
that.

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So, in this diagram here, we have a four
bit wide readout, or write, and we're

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going to have one, two, three, four, five,
six, seven, eight bits in, bits across

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here.
So we're gonna need a two to column

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decode.
So this is a one bit decode here.

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But as a, this is just a toy example.
As we go to build sort of 1000 bit arrays

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or megabyte arrays or gigabyte arrays or
giga-bit arrays we're gonna have lots of

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bits coming here and lots of bits there.
But the, the ideal one to get across is

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you split off a portion of the address to
the word-lied creation and a portion of

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the address to your column decode here.
And this register file, I wanted to just

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sort of walk through.
What this diagram over here, the circuit

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little diagram is.
Here we have two cross coupled inverters.

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And as you'll see we don't have full
complimentary logic connecting these two

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things, but this is, this is a stable
storage cell.

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If you give this power it'll store data.
If we wanna do a read, we need to connect

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to the output of this to read bit lines.
And these read bit lines are these

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vertical wires running here.
And we're gonna use, we're gonna do this

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with effectively a pass gate here.
When we energize the read word line, it

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connects the output of this gate or output
of, it's gonna be this inverter here to

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the read bit line.
And if we wanna do a write, we're going to

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turn on, not the read word line, RWL here.
But we're trying the write word line, WWL

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and what that's gonna do is it's going to
connect both the Q and Q bar to the right

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bit line.
And, now we get into this sorta some

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analog, magic here.
But, in order to have this work, what

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we're gonna do is we're gonna put, we're
gonna energize, or, or ground the write

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bit line so that it's stronger than what's
going on of these two, or stronger than

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what either of these inverters can drive.
So we overpower the inverter.

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And we can flip it, let's say from a zero
to one, or a one to a zero.

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So this is not traditional sort of
complementary logic, but this how we

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typically build register files.
Small little arrays that are close, let's

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say in to a processor.
Now, lets move to something, a little bit

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larger.
We are gonna look at, memory arrays.

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So, these are things like SRAMs.
So we go from register files, something

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that we'd hold our general purpose
register for processor in.

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And we are gonna move out a little bit and
talk about small arrays, something like

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caches, maybe a kilobyte of data, and
these are typically built out of SRAMs.

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Same structure, we're gonna change the
cell a little bit here.

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The main difference is the cell we're
gonna have two sets of bit lines.

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We're gonna have bit and bit bar.
And then we're gonna have two pass gates

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here and these are cross coupled inverters
in the middle.

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And by doing this, we also have this, this
word line running the other direction

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which connects this cross couple inverter
to the bit lines.

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By having these, SRAM arrays typically,
what happens is, because the, because you

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have bit and bit bar, you can have these
be even weaker than normal, and when you

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go to build something like an SRAM down
here, in addition to the column decode,

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you're also gonna have, a word called,
sunsamps.

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These are basically operational
amplifiers, where you hook the bits and

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the bit bar to them, and it can sense a
very small difference between the bit and

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bitbar.
And by doing this, you can effectively

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have a very low difference between bit and
bit bar, and be able to sense it at the,

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at the other side.
And one of the differentiations I wanted

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to make between a register file and this
SRAM here is that the register files, many

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times are designed to be sort of
multi-ported.

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But in this diagram here, these bit lines
get reused.

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They are both read and write bit lines.
So, we have effectively built a

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single-ported SRAM.
Having said that people do build

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multi-ported SRAMs, and single ported
register files, but conventionally you

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build a register file when you need speed
and you need lots of ports and you build

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an SRAM when you want to be more dense in
your storage.

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Okay, so now let's move to a piece of
technology which is in all of your

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computers or register files and SRAMs are
all in your computers, but this is

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something that you can actually like see.
'Cause usually the SRAMs and the register

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files are all integrated onto your
centralised microprocessor, you don't

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actually get to go, see it.
But here we have a stick of DRAM.

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So let's see what this is.
This is PC100 DRAM and this old stuff.

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This 128 megabytes of RAM.
Nowadays your computer has, at least this

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laptop here has four gigabytes of DRAM.
And different people have different

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amounts, but DRAM on the contrast with
SRAM, you still go and build an array out

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of it.
But the actual storage looks very

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different.
The bit cell storage, instead of being

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some form of cross coupled inverse.
Instead, you're gonna have one transistor

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which hooks a capacitor into your bit
line.

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Now you may ask yourself how do you build
a capacitor?

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The capacitor typically you'd need, you
know, two plates or two pieces of metal

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with some dielectric in the middle.
We can store charge.

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Well, what's inside of that RAM looks very
odd.

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It, it is a capacitor, but it's a very
oddly shaped capacitor.

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Typically what'll happen is you build
these very, very deep trenches very long

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and skinny trenches.
You want the skinny cause you wanna put

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them very close together, cause if you
want gigabytes of gigabytes of RAM, the

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smaller you make it, the more you can
shove on a, a single piece of silicon.

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But you have this really long and narrow
trenches here and you have two plates of

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metal and then a dielectric in the middle.
So in this case here, we have, I think,

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there's two metal sort of plates here and
then there's some dielectrics sort of

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shoved in between there, but you can't
really see it in this picture.

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And then all the actual logic, is up here.
So, in this diagram here, this is the

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transistor.
And [inaudible], and here's the, the,

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depletion region, here's our word line.
But basically, that's, that's this

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transistor here.
So, we're going to be connecting the

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capacitor which has a very funny aspect
ratio, very tall to this bit line.

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And to give you some idea.
This is a slice through the silicon wafer.

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This is not a plan view or top view.
Top view, you would just see the, looks

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like a transistor and then some poly plug
here running vertically it would look

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really small.
But this is a slice.

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And the reason we do this is cause we
wanna see that the actual capacitor is

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very long, very deep into this.
And what they want to point out is this is

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typically really hard to go build on your
standard CMOS process.

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So this is hard to go build on something a
logic process.

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You have to go build this, let's say, in a
special DRAM only manufacturing process.

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So you want a, it's sometimes hard to mix
that.

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There are some technologies which allow
you to mix them, but when you do that,

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people haven't really designed ways to
make them as small.

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But DRAMs cells are small.
Okay, so why, what are the advantages of

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DRAM?
Why are we even talking about DRAM?

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Well, it's a lot easier in DRAM to have
large amounts of storage.

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You can have big amounts of storage in the
same area.

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Because instead of having, I don't know,
in SRAM, six or eight transistors for each

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cell.
Instead, we now have one transistor and

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one capacitor.
So it's actually less.

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Now, how does this circuit work?
Well logically, what we're gonna do is

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we're gonna store data, or store charge in
the capacitor.

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So we're gonna connect to the capacitor to
the bit line.

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We're gonna either put a one or a zero on
the bit line.

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And then, we're gonna disconnect it and
it'll hopefully store the charge.

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And at some point in the future, we're
gonna connect it, and we're gonna

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discharge it into, the capacitor into the
bit line, and read out the value.

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And we still need something at the bottom
here, which is very sensitive to read out

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this bit.
And the reason is cause the capacitance

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that you can store in one of these little
capacitors is very small amounts, so

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there's a whole lot of charge in the, in
the circuit.

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Hm.
Okay.

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So what is the cell, what's, what's the
problems with this?

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Well, first, one of the major problems
with this, is you're gonna end up having

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this capacitor discharged and charged and
capacitors as you may recall, don't always

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store their charge, that well.
They might slowly, lose that charge, over

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time.
And what this turns out to be, is you're

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actually going to have to, refresh the
DRAM.

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So, you might have heard of DRAM refresh.
But typically, you know, in a modern,

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modern day computer, your, your DRAM will
only hold the data for, maybe a few

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seconds.
It used to be that it, it only held it for

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a few milliseconds.
Most RAM's actually decent now and you've

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probably seen some tacks, the people have
built around this.

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Like there's some encryption in tacks
where people will effectively turn off a

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computer and then pull the RAM out and
stick it in a different computer and the

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DRAM out and stick it in a different
computer.

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And the DRAM will still hold the charge,
still hold the information even if you

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remove the, the electricity or remove the
power from it because it's has a bunch of

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little capacitors that will store that
charge.

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That's, that's a funny little case with
this DRAM.

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Ends up being a negative.
But we're really doing this to have more,

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more space to, to, to store data, because
each of these bit cells is a lot smaller.

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Okay, so I like this diagram, this is, one
of the more key diagrams in today's

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lecture, here is, showing the relative
sizes of SRAM, versus DRAM, and different

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heights of SRAM versus DRAM.
So let's start off here with.

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An SRAM cell built out of logic, a logic
processor, logic CMOS technology.

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So that's, that's this one here.
This looks to be six transistors, so sort

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of optimized SRAM monologic process and
this is pretty big.

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Lets contrast that though, with this one
over here, we have DRAM on a memory

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specific process and it's tiny, so it's
not only one transistor versus six

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transistors.It's actually more than six
times smaller because they can optimize

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this.
They can go into the Z dimension here, go

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in out of the board.
Because, that's, that the trench capacitor

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goes down into the substrate.
And some of the other interesting things

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on, on this diagram here we have a DRAM on
an Asic process, or DRAM on a traditional

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Asic process, which is, which is here.
Here we have six transistor cell with

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local interconnect.
It's a little bit smaller, so what that

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means by local interconnect is you can use
polylayer of your process the poly silicon

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layer to do interconnections.
So you don't have to use wires for

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everything.
So it gets a little bit denser, the layout

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gets a little bit denser.
And I really like this bottom one here.

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Yep, the bottom one labeled A is not.
It's not four different things.

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Instead, what that is, this is a fully
complimentary logic cell, a storage cell

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built out of gates.
So, it's some number of gates put together

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here.
So, this is, what's this trying to get

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across here is, that the addition of
custom logic cells, here, this one this

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one, storage cells in your library is
really important.

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Because, otherwise your RAM's going to be
a lot, lot larger or you won't be able to

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fit as much memory on your machine.
Okay, so to wrap this memory technology

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section up, I wanna talk about some of the
tradeoffs.

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So in computer architecture is all about
the tradeoffs.

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And, why would we use one type of
technology versus another type of

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technology?
So, what are our tradeoffs here?

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Or we can go from fast, close, small
things.

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So things like latches and registers.
At least sort of put them together into

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bigger, we can put together bigger things
like something like a register file and

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then SRAM and have different technologies
even.

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And as we sort of get into bigger and
bigger memories, we got a lot more

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capacity, but it takes longer to access
them, kinda of definition And typically we

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have less bandwidth.
But if we have, small things, we have low

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capacity, low latency and very high
bandwidth.

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So it's sort of a tradeoff of capacity
versus the other positive aspects and

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depending on where you put it in your
memory system.

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You might want to trade these off