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Okay.
So let's.

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We're, we're almost to the end here le,
of, of control, hazards.

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Let's talk about why an instruction may
not be dispatched every cycle.

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Well.
Let's, let's think about forwarding and

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full bypassing.
This is sometimes really expensive to add.

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If you are gonna bypass every location in
your pipe, that may be expensive.

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So, we may still want to stop in certain
cases.

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A good example of this is, if you go look
at a modern day, something like your core

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I7 machine, they actually don't bypass
between all the different functional

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units, from all the different locations,
because they have, can execute about six

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instructions per cycle.
And there, they have many stages in the

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depth of their pipe, so they'd have to
basically be bypassing at a hundred

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different places for every new source off
branch.

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So, what you typically will do, is you'll
figure out, what are the common bypasses

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that are needed, are the common forwarding
paths that are needed and you'll have

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those.
And then some of the infrequently used

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ones, you just won't build.
This will help with your cycle time, but

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hurt with your CPI.
Loads, Can have a, or, typically have a

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2-cycle latency.
So we talked about this when we were

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talking about, load to use, and the
instruction after the load.

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Cannot necessarily use the result,
definitely cannot use the result because

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the in our five stage mix pipeline the
result is not computed into the memory

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stage, so if you are in the SQ stage you
would not have been able to get that even

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if you had bypassing out of the ends of
the load end of, end of the load pipe or

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to the end of the memory stage.
And one interesting thing is that the MIPS

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I Architecture.
Actually defines low delay slots, very

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similar to what we have in What, what,
what is what we had discussed with branch

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delay slots.
So MIPS I had load delay slots, which were

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software visible, Slots that you had to
fill and could solve, basically, this

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pipelining hazard.
And the compiler would have to schedule

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some non-dependent instruction.
So it was instruction which was not

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dependent on the load into that, that,
that spot.

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This was ultimately removed out of the ISA
and stalling was put back in cause as you

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went to different pipeline lanes and
different micro-architectures this, this

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started to, to be onerous.
And this is really one of the big problems

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with both load delay slots and branch
delay slots is it's not very

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micro-architecture independent.
So as you change to different micro

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architectures if you have let's say a
pipeline length of five and it went to

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four, all of sudden maybe you didn't need
that branch to lay slot or something,

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something like that.
And.

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I wanted to sort of point out here is,
this idea here, really is encapcilated in

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the name MIPS.
It stands for microprocessor without

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interlocked pipeline stages.
So, they really did not want to have

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interlocking here on something like the
load to use of that, and later in MIPS two

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that, that was removed in pipeline
interlocks were reintroduced.

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So, they, you know, we can all find
mistakes that we have done and, and have

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changed it, but in the original MIPS 1ISA
they had load delay slots.

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Another good reason why CPI might be
greater than one is we have conditional

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branches which can cause bubbles.
So this was all the control hazards we've

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been talking about up to this point, and
you may have to kill the instructions if

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you don't have some sort of delay slots.
Now, I wanted to point out here when we

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talk about cpi, and this is this note at
the bottom of the slide, is that you

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really wanna think about Cpi from the
perspective of a useable CPI, instead of

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How many instructions are executing.
So if you are adding no-ops to your

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program, and the no-ops are not doing
anything useful, that does not go into,

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that should not go into your useful CPI,
calculation.

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Your machine might count that as valid
instructions going down the pipe because

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you, it was software-invisible
instructions, but that's not a good

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solution.
What you should be computing in CPI, you

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should always be thinking about useful
CPI, or CPI that's actually towards the

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end-goal of the program.
Couple other control hazards That we need

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to talk about in this course are other
things that can change your control flow

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of your program.
And, those largely can fall into two

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different cases here.
Exceptions and interrupts.

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And they're both related.
And let's talk about what an exception is.

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So an exception is something where you
have an instruction And the instruction

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does some operation, which is invalid or
against what the intended use of

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machining.
So, a good example of this, a couple good

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examples, is divide by zero.
You take some value and divide it by zero.

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Well, on most computer architectures this
is ill-defined or undefined.

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So you'll actually get an exception, which
is a divide by zero error.

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And you can go try this out.
You can go log in to your computers, and

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go run a little C program.
Take some number, divide it by zero,

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you're going to get a div by zero error if
you're running on Linux.

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And get something similar if you're
running on Windows.

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And, Another good example of exceptions
is, things like a, memory fault.

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Your trying to access your not allowed to
go access.

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Some underflow and overflow exceptions in
certain architectures.

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If like number precision goes out of, out
of wack.

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If you have a, a, floating point number
becomes too large or too small, and the

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floating point arithmetic can't handle the
precision you'll sometimes get overflow

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and underflow exceptions.
And then it interrupts our external things

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happening.
And what's, So, something like a timer

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tick going off, or an IO device trying to
wake up your processor, or do something to

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your processor.
And why these are important, why these are

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control hazards, is these are unexpected
things, sort of, coming into the, the

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instruction stream, and it's going to
change.

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The subsequent instructions that are
executing so, but it really is a control

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hazard flow.
It's changing the program control flow.

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And we're going to be talking a lot more
about exceptions and interrupts, later in

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this course, but I just wanted to get this
idea across in this review so far that

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exceptions and interrupts are different
types of control flow hazards.